A computer system typically includes electronic components mounted on a motherboard. The motherboard includes a number of sockets configured to receive microprocessors sometimes referred to as a central processing units (CPUs). For instance, a dual-socket motherboard can be populated with one or two CPUs.
More recently, there has been an emphasis on the need to add programmable integrated circuits such as programmable logic devices (PLDs) to help improve the performance or processing capability of the computer system. One proposed solution involves encapsulating both a CPU and a PLD within a single multichip package, where the multichip package can then be inserted into an existing CPU socket. This multichip package (MCP) platform, however, is too limiting in terms of performance since it requires the CPU and the PLD to share a common cooling mechanism.
Another proposed solution involves forming PLDs on existing Peripheral Component Interconnect Express (PCIe) cards. These PCIe cards are coupled to one of the CPUs via a PCIe bus. In a multi-socketed system where two or more CPUs communicate with one another via a coherent low-latency CPU-to-CPU bus, it is challenging for the PLDs on the PCIe cards to communicate with the CPU-to-CPU bus, either because all the CPU-to-CPU links are already consumed by the microprocessors or because there is no natural communications path from the CPU-to-CPU bus onto the PCIe card.
It is within this context that the embodiments described herein arise.